ps2.c File Reference

PS/2 protocol implementation. More...

#include <inttypes.h>
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/pgmspace.h>
#include <stdio.h>
#include "ioconfig.h"
#include "ps2.h"

Include dependency graph for ps2.c:

Defines
#define	ps2_datin()   ((PS2PIN & _BV(PS2DAT)) ? 0200 : 0)
	Read PS2 data into bit 7.
#define	ps2_clkin()   ((PS2PIN & _BV(PS2CLK)) ? 0200 : 0)
	Read PS2 clk into bit 7.
Enumerations
enum	_state {   IDLE = 0, RX_DATA, RX_PARITY, RX_STOP,   TX_REQ0, TX_DATA, TX_PARITY, TX_STOP,   TX_ACK, TX_END, ERROR = 255 }
	PS2 protocol states. More...
Functions
void	ps2_dir (uint8_t, uint8_t)
	Set busses direction (1 == in).
void	ps2_clk (uint8_t)
	Set clk.
void	ps2_dat (uint8_t)
	Set dat.
uint8_t	ps2_busy ()
	Check if PS/2 statemachine is in IDLE state.
void	ps2_init ()
	Init PS/2 related I/O and interrupts.
void	ps2_recover ()
	Begin error recovery: disable reception and wait for timer interrupt.
void	ps2_enable_recv (uint8_t enable)
	Suspend or enable PS/2 device by pulling clock line low.
uint8_t	ps2_avail ()
	Check if the input buffer contains at least one byte.
uint8_t	ps2_getbyte ()
	Get one byte from input buffer. ps_avail() must be checked before doing so.
void	ps2_sendbyte (uint8_t byte)
	Transmit one byte and wait for completion.
	ISR (INT0_vect, ISR_NOBLOCK)
	ISR (TIMER0_OVF_vect)
	transmit timer and error recovery vector

---

Detailed Description

PS/2 protocol implementation.

This implementation is entirely interrupt-driven so all comms happens in background. Clock is tied to INT0 pin and events are handled in INT0 ISR handler.

Events not triggered by clock (end of transmission, transmission request, watchdog, error recovery) use Timer0. Watch out how state changes in different handlers.

---

Define Documentation

 

#define ps2_clkin

(

)

((PS2PIN & _BV(PS2CLK)) ? 0200 : 0)

Read PS2 clk into bit 7.

 

#define ps2_datin

(

)

((PS2PIN & _BV(PS2DAT)) ? 0200 : 0)

Read PS2 data into bit 7.

---

Enumeration Type Documentation

enum _state

PS2 protocol states.

Enumerator:

IDLE	Idle waiting.
RX_DATA	Receiving data.
RX_PARITY	Receiving parity bit.
RX_STOP	Receiving stop bit.
TX_REQ0	Requesting to send.
TX_DATA	Transmitting data.
TX_PARITY	Transmitting parity bit.
TX_STOP	Transmitting stop bit.
TX_ACK	Waiting ACK.
TX_END	Waiting for TX end.
ERROR	Error state.

            {
    IDLE = 0,           
    RX_DATA,            
    RX_PARITY,          
    RX_STOP,            
    
    TX_REQ0,            
    TX_DATA,            
    TX_PARITY,          
    TX_STOP,            
    TX_ACK,             
    TX_END,             
    
    ERROR = 255         
};

---

Function Documentation

ISR

(

TIMER0_OVF_vect

)

transmit timer and error recovery vector

                     {
    static uint8_t barkcnt = 0;
    
    switch (state) {
        case ERROR:
            state = IDLE;
            ps2_clk(0);
            ps2_dat(0);
            ps2_enable_recv(1);
            
            // stop timer
            TIMSK &= ~_BV(TOIE0);
            TCCR0 = 0;
            break;
        case TX_REQ0:
            // load the timer to serve as a watchdog
            // after 20 barks this is an error
            barkcnt = 20;
            TIMSK |= _BV(TOIE0);    // enable TMR0 interrupt
            TCNT0 = 0;//255;            // 20*255*256/8e6 == 163ms
            TCCR0 = 4;               // prescaler = /256, go!

            // waited for 100us after pulling clock low, pull data low
            ps2_dat(0);
            ps2_dir(0,0);
            
            // release the clock line
            ps2_dir(0,1); 
            
            GIFR |= _BV(INTF0); // clear INT0 flag
            GICR |= _BV(INT0);  // enable INT0 @(negedge clk)
                        
            // see you in INT0 handler
            bits = 8;
            parity = 0;

            state = TX_DATA;
            break;
        case TX_END:
            // wait until both clk and dat are up, that will be all
            if (ps2_clkin() && ps2_datin()) {
                TIMSK &= ~_BV(TOIE0);
                TCCR0 = 0;
                state = IDLE;
            } else {
                if (waitcnt == 0) {
                    state = ERROR;
                    ps2_recover();
                } else {
                    waitcnt--;
                }
            }
            break;
        default:
            // watchdog barked: probably not a mouse!
            if (barkcnt == 0) {
                state = ERROR;
                ps2_recover();
            } else {
                barkcnt--;
            }
            break;
    }
}

Here is the call graph for this function:

ISR	(	INT0_vect	,
		ISR_NOBLOCK
	)

Happens every negative PS2 clock transition.

ISR_NOBLOCK because nothing here is really critical, while C1351 emulation is really time critical.

                            {
    uint8_t ps2_indat = ps2_datin();
    switch (state) {
        case ERROR:
            break;  
            
            // Receive states
                      
        case IDLE:
            if (ps2_indat == 0) {
                state = RX_DATA;
                bits = 8;
                parity = 0;
                recv_byte = 0;
            } else {
                state = ERROR;
            }
            break;
        case RX_DATA:
            recv_byte = (recv_byte >> 1) | ps2_indat;
            parity ^= ps2_indat;
            
            if (--bits == 0) {
                state = RX_PARITY;
            }
            break;
        case RX_PARITY:
            parity ^= ps2_indat;
            if (parity) {
                state = RX_STOP;
            } else {
                state = ERROR;
            }
            break;
        case RX_STOP:
            if (!ps2_indat) {
                state = ERROR;
            } else {
                rx_buf[rx_head] = recv_byte;
                rx_head = (rx_head + 1) % PS2_RXBUF_LEN;
                
                state = IDLE;                
            }
            break;
            
            // Transmit states
            
        case TX_REQ0:
            // state will be switched in timer interrupt handler
            break;
        case TX_DATA:
            ps2_dat(tx_byte & 001);
            parity ^= tx_byte & 001;
            tx_byte >>= 1;
            if (--bits == 0) {
                state = TX_PARITY;
            }
            break;
        case TX_PARITY:
            ps2_dat(parity ^ 001);
            state = TX_STOP;            
            break;
        case TX_STOP:
            ps2_dat(0);
            ps2_dir(1,1);
            state = TX_ACK;         
            break;
        case TX_ACK:
            if (ps2_indat) {
                state = ERROR;
            } else {
                // this will end in TMR0 interrupt
                state = TX_END;                

                waitcnt = 50;           // after 100us it's an error
                TIMSK |= _BV(TOIE0);    // enable TMR0 interrupt
                TCNT0 = 255-2;              // 4 counts: 2us
                TCCR0 = 2;              // prescaler = f/8: go!
            }
            break;
        case TX_END:
            break;
    }
    ps2_recover();
}

Here is the call graph for this function:

uint8_t ps2_avail

(

)

Check if the input buffer contains at least one byte.

                    {
    return rx_head != rx_tail;
} 

uint8_t ps2_busy

(

)

Check if PS/2 statemachine is in IDLE state.

{ return state != IDLE; }

void ps2_clk

(

uint8_t

c

)

Set clk.

                        {
    c ? (PS2PORT |= _BV(PS2CLK)) : (PS2PORT &= ~_BV(PS2CLK));
}

void ps2_dat

(

uint8_t

d

)

Set dat.

                        {
    d ? (PS2PORT |= _BV(PS2DAT)) : (PS2PORT &= ~_BV(PS2DAT));
}

void ps2_dir	(	uint8_t	dat_in,
		uint8_t	clk_in
	)

Set busses direction (1 == in).

                                             {
    dat_in ? (PS2DDR &= ~_BV(PS2DAT)) : (PS2DDR |= _BV(PS2DAT));
    clk_in ? (PS2DDR &= ~_BV(PS2CLK)) : (PS2DDR |= _BV(PS2CLK));
}

void ps2_enable_recv

(

uint8_t

)

Suspend or enable PS/2 device by pulling clock line low.

Parameters:

1

= enable

                                     {
    if (enable) {
        state = IDLE;
        ps2_dir(1,1);
        // enable INT0 interruptt
        GIFR |= _BV(INTF0);
        GICR |= _BV(INT0);
    } else {
        // disable INT0, then everything else
        GICR &= ~_BV(INT0);
        ps2_clk(0);
        ps2_dir(1,0);
    }
}

Here is the call graph for this function:

uint8_t ps2_getbyte

(

)

Get one byte from input buffer. ps_avail() must be checked before doing so.

                      {
    uint8_t result = rx_buf[rx_tail];
    rx_tail = (rx_tail + 1) % PS2_RXBUF_LEN;
    
    return result;
}

void ps2_init

(

)

Init PS/2 related I/O and interrupts.

                {
    state = IDLE;
    rx_head = 0;
    rx_tail = 0;
    ps2_enable_recv(0);
    
    MCUCR |= _BV(ISC01); // falling edge for INT00
    TIMSK &= ~_BV(TOIE0);
}

Here is the call graph for this function:

void ps2_recover

(

)

Begin error recovery: disable reception and wait for timer interrupt.

                   {
    if (state == ERROR) {
        ps2_enable_recv(0);
        TCNT0 = 255-35; // approx 1ms
        TIMSK |= _BV(TOIE0);

        TCCR0 = 4;  // enable: clk/256
    }
}

Here is the call graph for this function:

void ps2_sendbyte

(

uint8_t

byte

)

Transmit one byte and wait for completion.

                                {
    while (state != IDLE);
     
    // 1. pull clk low for 100us
    ps2_enable_recv(0);

    tx_byte = byte;
    state = TX_REQ0;
    
    // 128us
    TCNT0 = 255-4; 
    TIMSK |= _BV(TOIE0);
    TCCR0 = 4;
    
    while (state != IDLE);
}

Here is the call graph for this function: