Superheterodyne VLF Receiver For Time Reference Stations


nixie tube This all started as a small and simple project that would eventually become a pretty Nixie clock. But making just a clock is not really all that challenging and noteworthy. So it has to be a radio-synchronized Nixie clock. Using a ready-made DCF77 module was out of question because I live where these modules are not guarranteed to work, are barely available, not too interesting to use ready-made modules anyway.

First attempt was a direct amplification receiver with I/Q demodulator. It was a moderate success, I could receive and decode MSF time code but in fact I had to manually retune the antenna and regeneration cascade every time I turned it on. Reception also was very poor, even when tuned. At best times, it was possible to receive sensible signal between 3 to 4 in the morning, and even that was not really guarranteed. So, building a superhet receiver was a next logical choice.


Every superhet needs a het. So this is where I began the development of my new make of the receiver. I had some samples handy, so the decision was to use AD9833 DDS chips as main source of LO frequency. Another DDS would provide IF frequency for baseband mixing for I/Q demodulation if the latter will be necessary. If it won't, another signal output is never really a disadvantage.

After the signal is mixed, filtered and amplified, it's supposed to return back, digitized and processed by the microcontroller. AVR devices I'm using typically have builtin ADC, but only one. Just in case I would need two separate channels for I/Q demodulation I decided to use two external ADC chips. This would allow me to clock them, and thus get the signals sampled, absolutely simultaneously.

The resulting mixed-signal board thus provides following units and features:

Work In Progress

Note: this isn't really a blog, so the updates appear at the bottom of the page. Bear with me.

As of July 17, 2006 this is what I have. Everything except the ADC's is already in place. Better part of firmware related to signal sourcing is written. ADC's are waiting for their turn. Here is how it looks now:

glamour photo

No, this is not Ethernet socket. It's an RS232 port, wired to Cisco console standard. And here's a little video demo of the UI. It's a huge challenge to make UI in Russian, we have very long words.

July 23, 2006

ADC's are alive and kicking. AD7478, or even its direct replacement part from National ADCS7478, work not bad at all. At first I tried to pump their SCK monotonously, at 16x the sample rate. But since my sample rate is very low, I started with 600Hz, it didn't meet the minimal sample rate requirement: the result was not beautiful. After I implemented burst mode, a series of very fast SCK pumped every 1/Fsamp, result has become excellent. Judge for yourself: this is a 20Hz sine wave fed from SBLive! rear channel output, sampled at 400SPS.

Here is the complete schematic in PDF file. This is the revised version that works.

Updated August 8, 2006i: 25MHz MCLK distribution is now more of a transmission line, nice fronts and just some 2.8Vp-p.

The Hetski is now ready. Next objective: the RF module!

August 8, 2006

With my new Tek scope a lot of things have become visible, many bad things too. Spent quite a while finding causes of glitches, learned interesting things about probes.. Filter your power kids, especially when it's from a switchmode supply like a Nokia phone charger.

Here's a neat trick you can do with a 2-channel DSO (at least with a 2-channel Tektronix DSO, not sure about the others). Suppose we have a stable, repetitive event that can be used as a sure mark. Then we can store 2 waveforms in Reference memory, display them and display 2 currently measured events. Thus we're getting 4 waveforms on one screen. Isn't that cool?

ADC access diagram

On this picture we can see (bottom to top):
Last updated: Tue Aug 8 18:01:27 MSD 2006
Back to svo's home